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9DB1233 idt ? t welve output dif ferential buf fer for pcie gen3 1675b ?1 1/08/10 t welve output differential buffer for pcie gen3 da t asheet 1 general descriptionoutput features the 9DB1233 zero-delay buffer supports pcie gen3requirements, while being backwards compatible to pcie gen2 and gen1. the 9DB1233 is dr iv en b y a diff erential src output pair from an idt 932s421 or 932sq420 or equivalent maincloc k gener ator . it atten uates jitter on the input cloc k and has a selectable pll bandwidth to maximize performance in systemswith or without spread-spectrum clocking. ? 12 - 0.7v current mode differential hcsl output pairs functional block diagram ke y specifications ? output cycle-cycle jitter < 50ps . ? output-to-output skew < 50 ps ? pcie gen3 phase jitter < 1.0ps rms ? pin compatib le with db1200 y ello w co v er de vice features/benefits? 3 selectable smbus addresses/mulitple devices can sharethe same smbus segment ? 12 oe# pins/hardware control of each output ? pll or bypass mode/pll can dejitter incoming clock ? selectable pll bandwidth/minimizes jitter peaking indownstream pll's ? spread spectrum compatible/tracks spreading input clockfor low emi ? smbus interface/unused outputs can be disabled ? suppor ts undr iv en diff erential outputs in p ow er do wn mode for power management recommended application12 output pcie gen3 zero-delay/fanout buffer dif_in dif_in# dif(11:0)) control logic bypass#/pll smbdat smbclk vttpwrgd#/pd spread compatible pll 12 iref oe_(11:0)# 12 high_bw# m u x adr_sel
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 2 1675b ?1 1/08/10 pin configuration vdd 1 64 vdda dif_in 2 63 agnd dif_in# 3 62 iref gnd 4 61 vdd oe0# 5 60 oe11# dif_0 6 59 dif_11 dif_0# 7 58 dif_11# vdd 8 57 vdd gnd 9 56 gnd oe1# 10 55 oe10# dif_1 11 54 dif_10 dif_1# 12 53 dif_10# oe2# 13 52 oe9# dif_2 14 51 dif_9 dif_2# 15 50 dif_9# gnd 16 49 gnd vdd 17 48 vdd oe3# 18 47 oe8# dif_3 19 46 dif_8 dif_3# 20 45 dif_8# oe4# 21 44 oe7# dif_4 22 43 dif_7 dif_4# 23 42 dif_7# vdd 24 41 vdd gnd 25 40 gnd oe5# 26 39 oe6# dif_5 27 38 dif_6 dif_5# 28 37 dif_6# **adr_sel 29 36 vttpwrgd#/pd high_bw# 30 35 bypass#/pll vdd 31 34 gnd smbclk 32 33 smbdat 64-tssop ** indicates 120k ohm pulldown 9DB1233 power groups vdd gnd 1 4 dif_in/dif_in# 8, 17, 24, 41, 48, 57 9, 16, 25, 40, 49, 56 dif(11:0) n/a 63 iref 64 63 analog vdd & gnd for pll core note: please treat pin 1 as an analog vdd. description pin number smbus address selection (pin 29) adr_sel voltage smbus adr (wr/rd) low <0.8v dc/dd mid 1.2 2.0v d4/d5
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 3 1675b ?1 1/08/10 pin description pin # pin name type description 1 vdd pwr power supply, nominal 3.3v 2 dif_in in 0.7 v differential true input 3 dif_in# in 0.7 v differential complementary input 4 gnd pwr ground pin. 5 oe0# in active low input for enabling dif pair 0. 1 =disable outputs, 0 = enable outputs 6 dif_0 out 0.7v differential true clock output 7 dif_0# out 0.7v differential complementary clock out put 8 vdd pwr power supply, nominal 3.3v 9 gnd pwr ground pin. 10 oe1# in active low input for enabling dif pair 1. 1 =disable outputs, 0 = enable outputs 11 dif_1 out 0.7v differential true clock output 12 dif_1# out 0.7v differential complementary clock ou tput 13 oe2# in active low input for enabling dif pair 2. 1 =disable outputs, 0 = enable outputs 14 dif_2 out 0.7v differential true clock output 15 dif_2# out 0.7v differential complementary clock ou tput 16 gnd pwr ground pin. 17 vdd pwr power supply, nominal 3.3v 18 oe3# in active low input for enabling dif pair 3. 1 =disable outputs, 0 = enable outputs 19 dif_3 out 0.7v differential true clock output 20 dif_3# out 0.7v differential complementary clock ou tput 21 oe4# in active low input for enabling dif pair 4 1 =disable outputs, 0 = enable outputs 22 dif_4 out 0.7v differential true clock output 23 dif_4# out 0.7v differential complementary clock ou tput 24 vdd pwr power supply, nominal 3.3v 25 gnd pwr ground pin. 26 oe5# in active low input for enabling dif pair 5. 1 =disable outputs, 0 = enable outputs 27 dif_5 out 0.7v differential true clock output 28 dif_5# out 0.7v differential complementary clock ou tput 29 **adr_sel in this tri-level input selects one of 3 smbus address es. see the smbus address select table for the addresses. 30 high_bw# in 3.3v input for selecting pll band width 0 = high, 1= low 31 vdd pwr power supply, nominal 3.3v 32 smbclk in clock pin of smbus circuitry, 5v tolerant
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 4 1675b ?1 1/08/10 pin description (cont.) pin # pin name type description 33 smbdat i/o data pin of smbus circuitry, 5v tolerant 34 gnd pwr ground pin. 35 bypass#/pll in input to select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 36 vttpwrgd#/pd in vttpwrgd# is an active low input used to sample lat ched inputs and allow the device to power up. pd is an asynchronous active high input pin used to put the device into a low power state. the internal clocks and plls are stopped. 37 dif_6# out 0.7v differential complementary clock ou tput 38 dif_6 out 0.7v differential true clock output 39 oe6# in active low input for enabling dif pair 6. 1 =disable outputs, 0 = enable outputs 40 gnd pwr ground pin. 41 vdd pwr power supply, nominal 3.3v 42 dif_7# out 0.7v differential complementary clock ou tput 43 dif_7 out 0.7v differential true clock output 44 oe7# in active low input for enabling dif pair 7. 1 =disable outputs, 0 = enable outputs 45 dif_8# out 0.7v differential complementary clock ou tput 46 dif_8 out 0.7v differential true clock output 47 oe8# in active low input for enabling dif pair 8. 1 =disable outputs, 0 = enable outputs 48 vdd pwr power supply, nominal 3.3v 49 gnd pwr ground pin. 50 dif_9# out 0.7v differential complementary clock ou tput 51 dif_9 out 0.7v differential true clock output 52 oe9# in active low input for enabling dif pair 9. 1 =disable outputs, 0 = enable outputs 53 dif_10# out 0.7v differential complementary clock o utput 54 dif_10 out 0.7v differential true clock output 55 oe10# in active low input for enabling dif pair 10. 1 =disable outputs, 0 = enable outputs 56 gnd pwr ground pin. 57 vdd pwr power supply, nominal 3.3v 58 dif_11# out 0.7v differential complementary clock o utput 59 dif_11 out 0.7v differential true clock output 60 oe11# in active low input for enabling dif pair 11. 1 =disable outputs, 0 = enable outputs 61 vdd pwr power supply, nominal 3.3v 62 iref out this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed preci sion resistor tied to ground in order to establish the appropriate curren t. 475 ohms is the standard value. 63 agnd pwr analog ground pin for core pll 64 vdda pwr 3.3v power for the pll core.
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 5 1675b ?1 1/08/10 electrical characteristics - absolute maximum ratin gs parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. electrical characteristics - input/supply/common pa rameters ta = t com ; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes ambient operating temperature t com commmercial range 0 70 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2 v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 f ibyp v dd = 3.3 v, bypass mode 10 166 mhz 2 f ipll v dd = 3.3 v, 100mhz pll mode 90 100.00 110 mhz 2 pin inductance l pin 7 nh 1 c in logic inputs, except dif_in 1.5 5 pf 1 c indif_in dif_in differential clock inputs 1.5 5 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1.8 ms 1,2 input ss modulation frequency f modin allowable frequency (triangular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 4 12 cycles 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 5 ns 1,2 trise t r rise time of control inputs 5 ns 1,2 smbus input low voltage v ilsmb 0.8 v 1 smbus input high voltage v ihsmb 2.1 v ddsmb v 1 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4 ma 1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 5 the differential input clock must be running for th e smbus to be active input current 3 time from deassertion until outputs are >200 mv 4 dif_in input capacitance input frequency
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 6 1675b ?1 1/08/10 electrical characteristics - clock input parameters ta = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v ihdif differential inputs (single-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j difin differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero electrical characteristics - dif 0.7v current mode differential outputs t a = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes slew rate trf scope averaging on 1 2.4 4 v/ns 1, 2, 3 slew rate matching ? trf slew rate matching, scope averaging on 20 % 1, 2, 4 voltage high vhigh 660 800 850 1 voltage low vlow -150 20 150 1 max voltage vmax 850 1150 1 min voltage vmin -300 1 vswing vswing scope averaging off 300 mv 1, 2 crossing voltage (abs) vcross_abs scope averaging off 250 550 mv 1, 5 crossing voltage (var) ? -vcross scope averaging off 140 mv 1, 6 2 measured from differential waveform 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential rising edge (i.e. clock rising and clock# falling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset o f v_cross_min/max (v_cross absolute) allowed. the intent is to limit vcross induced modu lation by setting v_cross_delta to be smaller than v_cross absolute. mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. iref = vdd/(3xr r ). for r r = 475 (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 (100 differential impedance). 3 slew rate is measured through the vswing voltage ra nge centered around differential 0v. this results in a +/-150mv window around differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calcula te the voltage thresholds the oscilloscope is to use for the edge rate calculatio ns. electrical characteristics - current consumption ta = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes operating supply current i dd3.3op all outputs active @100mhz, c l = full load; 300 375 ma 1 i dd3.3pd all diff pairs driven ma 1 i dd3.3pdz all differential pairs tri-stated 21 24 ma 1 1 guaranteed by design and characterization, not 100% tested in production. powerdown current na
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 7 1675b ?1 1/08/10 electrical characteristics - output duty cycle, jit ter, skew and pll characterisitics ta = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes -3db point in high bw mode 2 3 4 mhz 1 -3db point in low bw mode 0.7 1 1.4 mhz 1 pll jitter peaking t jpeak peak pass band gain 1.5 2 db 1 duty cycle t dc measured differentially, pll mode 45 49.5 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -2 0 2 % 1, 4 t pdbyp bypass mode, v t = 50% 2500 4500 ps 1 t pdpll pll mode v t = 50% -250 250 ps 1 skew, output to output t sk3 v t = 50% 45 50 ps 1 pll mode 25 50 ps 1,3 additive jitter in bypass mode 25 50 ps 1,3 1 guaranteed by design and characterization, not 100% tested in production. 2 i ref = v dd /(3xr r ). for r r = 475 (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 . 3 measured from differential waveform 4 duty cycle distortion is the difference in duty cy cle between the output and the input clock when the device is operated in bypass mode. skew, input to output jitter, cycle to cycle t jcyc-cyc pll bandwidth bw electrical characteristics - pcie phase jitter para meters ta = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes t jphpcieg1 pcie gen 1 34 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 1.1 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.2 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.4 1 ps (rms) 1,2,4,5 t jphpcieg1 pcie gen 1 2 5 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.5 0.6 ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.8 1 ps (rms) 1,2,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.35 0.5 ps (rms) 1,2,4,5, 6 1 applies to all outputs when driven by 932sq420dglf or equivalent. 6 for rms figures, additive jitter is calculated by solving the following equation: (additive jitter) = sqrt{(total jittter)^2 - (input jitter)^2} 4 subject to final radification by pci sig. t jphpcieg2 2 see http://www.pcisig.com for complete specs t jphpcieg2 phase jitter, pll mode additive phase jitter, bypass mode 5 calculated from intel-supplied clock jitter tool v 1.6.4 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12.
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 8 1675b ?1 1/08/10 clock periods differential outputs with spread spec trum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term average long-term average period long-term average short-term average period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum dif dif 100 9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.176 30 ns 1,2,3 clock periods differential outputs with spread spec trum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term average long-term average period long-term average short-term average period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum dif dif 100 9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2,3 1 guaranteed by design and characterization, not 100% tested in production. 3 driven by src output of main clock, pll or bypass mode measurement window symbol 2 all long term accuracy specifications are guarantee d with the assumption that the input clock complies with ck410b+/ck420bq accuracy requirements. the 9DB1233 itself does not contribute to ppm error. notes notes definition measurement window units symbol definition units
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 9 1675b ?1 1/08/10 common recommendations for differential routing dime nsion or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max i nch 1 l2 length, route as non-coupled 50ohm trace 0.2 max i nch 1 l3 length, route as non-coupled 50ohm trace 0.2 max i nch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm diffe rential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differ ential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm diffe rential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differ ential trace 0.225 min to 12.6 max inch 2 dif reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 10 1675b ?1 1/08/10 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compati ble 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common d ifferential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4)
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 11 1675b ?1 1/08/10 general smbus serial interface information for the 9DB1233 ho w to write: ? controller (host) sends a star t bit. ? controller (host) sends the write address dc (h) ? idt clock will acknowledge ? controller (host) sends the begining byte location = n ? idt clock will acknowledge ? controller (host) sends the data byte count = x ? idt clock will acknowledge ? controller (host) star ts sending byte n thr ough byte n + x -1 ? idt clock will acknowledge each byte one at a time ? controller (host) sends a stop bit ho w to read: ? controller (host) will send star t bit. ? controller (host) sends the write address dc (h) ? idt clock will acknowledge ? controller (host) sends the begining bytelocation = n ? idt clock will acknowledge ? controller (host) will send a separ ate star t bit. ? controller (host) sends the read address dd (h) ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n + x -1 ? idt clock sends byte 0 through byte x (if x (h) was written to b yte 8) . ? controller (host) will need to ac kno wledge each b yte ? controllor (host) will send a not ac kno wledge bit ? controller (host) will send a stop bit idt (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address dc (h) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge p stop bit idt (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address dd (h) index block read operation slave address dc (h) beginning byte = n ack ack note: addresses sho w assumes pin 29 is lo w.
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 12 1675b ?1 1/08/10 smbus table: frequency select register pin # name control function type 0 1 default bit 7 high_bw# high or low bw rw high bw low bw latch bit 6 bypass#/pll bypass (non-pll mode) or pll mode rw bypass pll latch bit 5 reserved reserved rw x bit 4 reserved reserved rw x bit 3 reserved reserved rw x bit 2 reserved reserved rw 1 bit 1 reserved reserved rw 0 bit 0 reserved reserved rw 1 smbus table: output control register pin # name control function type 0 1 default bit 7 dif_7 output control (disable = hi-z) rw disable enable 1 bit 6 dif_6 output control (disable = hi-z) rw disable enable 1 bit 5 dif_5 output control (disable = hi-z) rw disable enable 1 bit 4 dif_4 output control (disable = hi-z) rw disable enable 1 bit 3 dif_3 output control (disable = hi-z) rw disable enable 1 bit 2 dif_2 output control (disable = hi-z) rw disable enable 1 bit 1 dif_1 output control (disable = hi-z) rw disable enable 1 bit 0 dif_0 output control (disable = hi-z) rw disable enable 1 smbus table: output control register pin # name control function type 0 1 default bit 7 reserved reserved rw 0 bit 6 reserved reserved rw 0 bit 5 reserved reserved rw 0 bit 4 reserved reserved rw 0 bit 3 dif_11 output control (disable = hi-z) rw disable enable 1 bit 2 dif_10 output control (disable = hi-z) rw disable enable 1 bit 1 dif_9 output control (disable = hi-z) rw disable enable 1 bit 0 dif_8 output control (disable = hi-z) rw disable enable 1 smbus table: output enable readback pin # name control function type 0 1 default bit 7 oe7# oe# pin readback r enabled disabled x bit 6 oe6# oe# pin readback r enabled disabled x bit 5 oe5# oe# pin readback r enabled disabled x bit 4 oe4# oe# pin readback r enabled disabled x bit 3 oe3# oe# pin readback r enabled disabled x bit 2 oe2# oe# pin readback r enabled disabled x bit 1 oe1# oe# pin readback r enabled disabled x bit 0 oe0# oe# pin readback r enabled disabled x - - reserved byte 0 - - reserved - - - reserved - reserved reserved reserved byte 1 43,42 38,37 27,28 22,23 19,20 14,15 11,12 6,7 byte 2 - - - - 58,59 53,54 38,37 50,51 45,46 byte 3 43,42 27,28 22,23 19,20 14,15 11,12 reserved reserved reserved reserved 6,7
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 13 1675b ?1 1/08/10 smbus table: output enable readback pin # name control function type 0 1 default bit 7 reserved reserved r 0 bit 6 reserved reserved r 0 bit 5 reserved reserved r 0 bit 4 reserved reserved r 0 bit 3 oe11# output control (disable = hi-z) r enabled disabled x bit 2 oe10# output control (disable = hi-z) r enabled disabled x bit 1 oe9# output control (disable = hi-z) r enabled disabled x bit 0 oe8# output control (disable = hi-z) r enabled disabled x note: for an output to be enabled, both the output enable bit and the oe# pin must be enabled. this means that the output enable bit must be '1' a nd the corresponding oe# pin must be '0'. smbus table: vendor & revision id register pin # name control function type 0 1 default bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 1 bit 4 rid0 r - - 0 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbus table: device id pin # name control function type 0 1 default bit 7 rw 1 bit 6 rw 1 bit 5 rw 0 bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 0 bit 0 rw 0 smbus table: byte count register pin # name control function type 0 1 default bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 - reserved reserved - reserved byte 5 50,51 45,46 - - revision id - - - - vendor id - - - - - - - - byte 6 - - - byte 7 - writing to this register configures how many bytes will be read back. - - - - - - - device id 1 device id 6 device id 7 (msb) device id is c0 hex device id 5 device id 4 device id 3 device id 0 device id 2 reserved 58,59 53,54 byte 4 -
idt ? t welve output dif ferential buf fer for pcie gen3 9DB1233 t welve output diff erential buff er f or pcie gen3 14 1675b ?1 1/08/10 indexarea 1 2 n d e1 e a seating plane a1 a a2 e - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 de e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 64 16.90 17.10 .665 .673 10-0039 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (2 0 mil) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153 ordering information part / order number shipping packaging package tempera ture 9DB1233aglf tubes 64-pin tssop 0 to +70c 9DB1233aglft tape and reel 64-pin tssop 0 to +70c ?lf? after the package code denotes the pb-free con figuration, rohs compliant. ?a? is the device revision designator (will not cor relate with the datasheet revision).
9DB1233 t welve output diff erential buff er f or pcie gen3 15 innovate with idt and accelerate your future networks. cont act: www .idt .com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for t ech support 408-284-6578 pcclockhelp@id t.com corporate headquarters integrated device t echnology , inc. 6024 silver creek v alley road san jose, ca 95138 united s t ates 800 345 7015 +408 284 8200 (out side u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device t echnology , inc. all right s reserved. product specifications subject to change without notice. idt , ics, and the idt logo are trademarks of integrated device t echnology , inc. accelerated thinking is a service mark of integrated device t echnology , inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. issue date who description page # 0.1 7/7/2010 rdw initial release - a 7/12/2010 rdw 1. changed 'pwd' to 'default' in smbus 2. updated electrical tables 3. move to final 12,13 b 11/4/2010 rdw 1. corrected additive phase jitter calculation in p cie phase jitter table 2. added footnotes 5 and 6 to this table.

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